View MB40D001PFV_1274551.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS04-13514-2E
Linear IC Converter
CMOS
D/A Converter for Digital Tuning
MB40D001
s DESCRIPTION
The MB40D001 is an 8-bit D/A converter with 12 built-in channels. The 12 sets of analog outputs have built-in OP amps to enable use with large current drive applications. CS (chip select) data input/output format is used to enable connection to a serial bus. A built-in 12-bit I/O expander provides serial <=> parallel conversion (8 of the 12 bits are also used with analog output). The MB40D001 can be adapted for microcontroller port expansion, or replacement of electronic volume control or semi-fixed calibration resistance. Also, the MB40D001 is function- and pin-compatible with the MB88146A, for easy replacement when reducing sysytem operating voltage.
s FEATURES
* * * * * * * * * * Supply voltage 2.7 V to 3.6 V (Power consumption 0.7 mW/ch typ.) Compact package: SSOP-24 R-2R type 8-bit D/A converter with 12 built-in channels Built-in 12-bit I/O expander (8 of 12 bits also used with analog output) Built-in analog amplifier (sink current max. 0.4 mA, source current max. 1.0 mA) Built-in power-on detector circuit (detects VccD power-on, and performs initialization) Separate MCU interface power supply (VccD), OP amp supply (VccA), D/A converter supply VDD Analog output range 0 V to VccA. Serial data input/output operation to maximum of 2.5 MHz (1.5 MHz in cascade operation) CMOS process
s PACKAGES
24-pin plastic SSOP
(FPT-24P-M03)
MB40D001
s PIN ASSIGNMENT
(TOP VIEW)
AO1 AO2 AO3 AO4 D11/AO5 D10/AO6 D9/AO7 D8/AO8 D7/AO9 D6/AO10 D5/AO11 D4/AO12 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 GND VCCA CS SO SI CLK D0 D1 D2 D3 VCCD VDD
SSOP-24
19 18 17 16 15 14 13
(FPT-24P-M03)
2
MB40D001
s PIN DESCRIPTION
Pin no. 1 to 4 5 to 12 Symbol AO1 to AO4 D11/AO5 to D4/AO12 Description D/A converter analog output pins (VDD-GND output). (Default state: #00 setting level output) I/O expander parallel I/O pins (VccA/GND output 0.5 VccA/0.2 VccA input), also used as D/A converter analog output pins (VDD - GND output). Pin state is controlled by input data. See "Data Configuration". (Default state: Input mode, high-impedance state.) D/A converter reference power supply pin. MCU interface power supply (Power supply for I/O expander). I/O expander parallel I/O pins (VccD/GND output 0.5 VccD/0.2VccD input). Pin state is controlled by input data. See "Data Configuration". (Default state: Input mode, high-impedance state.) Shift clock input pin. When CS = "L", SI data is loaded into the shift register at the rise of the shift clock signal. Data input pin (serial input pin). Used for 16-bit serial data input. Data output pin (serial output pin). First-bit (LSB) data from the 16-bit shift register is output in synchronization with the fall of the shift clock signal. When CS = "H", this pin is in high impedance state. Chip select signal input pin. Input to shift registers is enabled when the CS signal falling edges. Shift register contents can be executed when the CS signal rising edges. Analog unit power supply pin (Power supply for the OP amp.). Common GND pin.
13 14 15 to 18
VDD*1 VCCD*1 D3 to D0
19
CLK*2
20 21
SI*2 SO
22
CS*2
23 24
VCCA*1 GND
*1: Be sure that VCCA VCCD, and that VCCA VDD. *2: Do not leave this pin in floating state.
3
MB40D001
s BLOCK DIAGRAM
CS SI CLK VCCD DF DE DD DC
16-bit shift resister & controller
DB BA D9 D8 D7 D6 D5 D4 CNTL
SO
DF
DE
DD
DC
DB
BA
D9
D8 DF
D7 DE
D6
D5 D5
D4 D4 12
D0 D1 D2 D3
I/O expander Data bus
DF
D8
DF
D8
DF
D8
DF
D8
8-bit latch
DF VDD D8 DF
8-bit latch
D8 DF
8-bit latch
D8 DF
8-bit latch
D8
R - 2R Ladder circuit
- + -
R - 2R Ladder circuit
+ -
R - 2R Ladder circuit
+ -
R - 2R Ladder circuit
+ GND
VCCA
8
AO1
AO4
D11/AO5
D4/AO12
4
MB40D001
s DATA CONFIGURATION
1. Data Configuration
MSB (last) LSB (first)
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Setting data Channel select
2. Channel Select
D3 0 0 0 to 1 1 1 1 1 D2 0 0 0 to 0 1 1 1 1 D1 0 0 1 to 1 0 0 1 1 D0 0 1 0 to 1 0 1 0 1 Don't Care/special function AO1 selected AO2 selected to AO11 selected AO12 selected I/O expander (serial parallel) I/O expander (parallel serial) Expander status register (ESR) Function
5
MB40D001
3. Setting Data
* Don't Care/special function (Channel select = "0000") DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 x to x 0 0 0 to 1 1 x x x x to x 0 0 0 to 1 1 x x x x to x 0 0 0 to 1 1 x x x x to x 0 0 0 to 1 1 x x x x to x 0 0 0 to 1 1 x x x x to x 0 0 0 to 1 1 x x x x to x 0 0 1 to 1 1 x x x x to x 0 1 0 to 0 1 x x x 0 to 1 1 1 1 to 1 1 1 1 1 0 to 0 1 1 1 to 1 1 1 1 1 0 to 1 0 0 0 to 0 0 0 1 1 0 to 1 0 0 0 to 0 0 1 0 1 Analog output voltage level Don't Care Don't Care Don't Care GND (all channels) VDD/256 x 1 (all channels) VDD/256 x 2 (all channels) to VDD/256 x 254 (all channels) VDD/256 x 255 (all channels) High impedance (I/O expander state)* Reset (state when power is ON) Don't Care
x: Don't care *: Hi-Z output on all channels of AO5 through AO12 * D/A Converter (Channel select = "0001" to "1100") DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 0 0 0 0 to 1 1 1 x x to x 0 0 0 0 to 1 1 1 x x to x 0 0 0 0 to 1 1 1 x x to x 0 0 0 0 to 1 1 1 x x to x 0 0 0 0 to 1 1 1 x x to x 0 0 0 0 to 1 1 1 x x to x 0 0 1 1 to 0 1 1 x x to x 0 1 0 1 to 1 0 1 x x to x 0 0 0 0 to 0 0 0 0 0 to 1 0 0 0 0 to 0 0 0 0 0 to 1 0 0 0 0 to 0 0 0 0 1 to 1 0 0 0 0 to 0 0 0 1 0 to 1 GND VDD/256 x 1 VDD/256 x 2 VDD/256 x 3 to VDD/256 x 253 VDD/256 x 254 VDD/256 x 255 High impedance (I/O expander state)* Don't Care Don't Care Don't Care Analog output voltage level
x: Don't care *: Only AO5 through AO12 output is valid
6
MB40D001
* I/O Expander [Channel select = "1101"]: Serial Parallel Conversion Performs parallel conversion of data bits D4 to DF for output on pins D0 to D11. Note that only those pins designated for output in the ESR (expander status register) are output. Shift register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Parallel I/O pins (output state) D11 D10
* I/O Expander [Channel select = "1110"]: Parallel Serial Conversion Writes data from D0 to D11 pins to bits D4 to DF in the shift register. Data is output to the SO pin on the shift clock (CLK) signal (The first 4 bits output data D0 to D3, so the converted output should be read as data bits 5 through 16.). Note that the data value is "0" for pins designated for output in the ESR (expander status register) as well as analog output pins. Shift register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Parallel I/O pins (output state) D11 D10
* Expander Status Register [Channel select = "1111"] Shift register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 ESR
This register sets the status of each pin.
Setting "0" "1"
Pin status * Input standby status (Hi-Z output) * D11 to D4 pins used for analog output should be set to "0". * Output state
7
MB40D001
Note: After power VCCD is turned ON (or after a reset), the state of pins and registers is as follows. Pin AO1 to AO4 D11/AO5 to D4/AO12 D3 to D0 Register Shift register D/A register Parallel output register All reset to "0". Not defined (retain prior state). "L" output Hi-Z state (input state) Hi-Z state (input state) State Bits DF to D8 are "0," and D7 to D0 are not defined (retain prior state). State
Expander status register (ESR) All reset to "0". * ESR settings have priority in determining pin states. Switching between input standby state and analog output state is enabled even when the ESR value is "1". When the ESR value returns to "0", the pin returns to its previously defined state. In input standby state with AO set for Hi-Z output, the AO output setting can be used for transition to AO output state.
8
MB40D001
s ABSOLUTE MAXIMUM RATINGS
Parameter Symbol VCCA Power supply voltage Input voltage 1 Output voltage 1 Input voltage 2 Output voltage 2 Power consumption Operating temperature Storage temperature * : VCCA VDD WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. VCCD VDD Vin1 Vout1 Vin2 Vout2 PD Ta Tstg SI, CLK, CS, SO, D0 to D3 D4 to D11 -- -- -- Based on GND (Ta = +25C) Conditions Rating Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- -20 -55 Max. +7.0 +7.0 VCCA* VCCD + 0.3 VCCD + 0.3 VCCA + 0.3 VCCA + 0.3 250 +85 +150 Unit V V V V V V V mW C C
s RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VCCA Power supply voltage VCCD VDD GND Analog output current Oscillation limit output capacity Operation temperature IAL IAH COL Ta Conditions -- -- VCCA VDD -- Source current Sink current -- -- Value Min. 2.7 2.7 2.0 -- -- -- -- -20 Typ. 3.0 -- -- 0 -- -- -- -- Max. 3.6 3.6 VCCA -- 1.0 0.4 1.0 +85 Unit V V V V mA mA F C
Note: Data in registers is retained in standby mode (digital supply: VccD voltage, analog supply: GND). WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
9
MB40D001
s ELECTRICAL CHARACTERISTIC
1. DC Characteristics
(1) Digital section Parameter Power supply voltage Power supply current Standby current Input leak current "H" level input voltage "L" level input voltage Output high-impedance leakage current "H" level output voltage "L" level output voltage Symbol Pin name VCCD ICCD VCCD ICCS IILK1 VIH1 VIL1 IOLK VOH1 VOL1 CLK, SI, CS, D0 to D3 SO SO, D0 to D3 Conditions -- CLK =1 MHz, (Unloaded) CLK, SI, CS Stop Vin = VCCD or GND Vin = 0 to VCCD -- -- Vin = 0 to VCCD IOH = -0.4 mA IOL = 2.5 mA Value Min. 2.7 -- -10 -10 0.5 x VCCD -- -10 VCCD - 0.4 -- Typ. 3.0 0.1 -- -- -- -- -- -- -- Max. 3.6 0.35 +10 +10 -- 0.2 x VCCD +10 -- 0.4 Unit V mA A A V V A V V
(2) D/A converter section Parameter Power supply voltage Power supply current Resolution Monotonic increase Nonlinearity error Differential linearity error Nonlinearity error: Symbol VDD IDD Res Rem LE DLE AO1 to AO12 Unloaded Pin name VDD Conditions VDD VCCA VDD VCCA Value Min. 2.0 -- -- -- -1.5 -1.0 Typ. 3.0 0.7 8 8 -- -- Max. 3.6 1.9 -- -- +1.5 +1.0 Unit V mA bit bit LSB LSB
Deviation (error) in input/output curves with respect to an ideal straight line connecting output voltage at "05" and output voltage at "FA". Deviation (error) in amplification with respect to theoretical increase in amplification per 1-bit increase in digital value.
Analog output
VAOH
Ideal line
Differential linearity error:
Nonlinearity error
VAOL
#05
#FA
Digital setting
Note:The value of VAOH and VDD, and the value of VAOL and GND are not necessarily equivalent.
10
MB40D001
(3) Operational Amplifier/Analog output section Parameter Power supply voltage Power supply current Input leakage current "H" level digital input voltage "L" level digital input voltage "H" level digital output voltage "L" level digital output voltage Analog output minimum voltage 1 Analog output minimum voltage 2 Analog output minimum voltage 3 Analog output minimum voltage 4 Analog output maximum voltage 1 Analog output maximum voltage 2 Analog output maximum voltage 3 Analog output maximum voltage 4 Symbol Pin name VCCA ICCA IILK2 VIH2 VIL2 VOH2 VOL2 VAOL1 VAOL2 AO1 to AO12 VAOL3 VAOL4 VAOH1 VAOH2 AO1 to AO12 VAOH3 VAOH4 D4 to D11 VCCA Conditions -- #80 setting (Unloaded) Vin = 0 to VCCA -- -- IOH = -0.4 mA IOL = 2.5 mA IAL = 0 A #00 setting IAL = 0.5 mA #00 setting IAH = 0.4 mA #00 setting IAL = 1.0 mA #00 setting IAL = 0 A #FF setting IAL = 0.5 mA #FF setting IAH = 0.4 mA #FF setting IAL = 1.0 mA #FF setting Value Min. 2.7 -- -10 0.5 x VCCA -- VCCA - 0.4 -- GND -0.2 GND -0.3 VCCA - 0.1 VCCA - 0.2 VCCA - 0.15 VCCA - 0.3 Typ. 3.0 1.0 -- -- -- -- -- -- GND -- GND -- -- VCCA -- Max. 3.6 4.8 +10 -- 0.2 x VCCA -- 0.4 0.1 0.2 0.15 0.3 VCCA VCCA VCCA + 0.15 VCCA Unit V mA A V V V V V V V V V V V V
Note: IAH: Analog output sink current IAL: Analog output source current
11
MB40D001
2. AC Characteristics
Parameter Clock "L" level pulse width Clock "H" level pulse width Clock rise time Clock fall time Serial input setup time Serial input hold time Serial output delay time CS input setup time CS hold time CS "H" level hold time Data output enable time Data output float time Parallel input setup time Parallel input hold time Parallel output delay time Analog output delay time Power supply rise time Power-on reset non-startup power supply variation Symbol tCKL tCKH tCr tCf tSSU tSHD tSOD tCSU tCCH tCSH tSO tSOZ tPSU tPHD tPOD tAOD tR VR Conditions -- -- -- -- -- -- See "Load condition 1"* -- -- -- -- -- -- -- See "Load condition 1" See "Load condition 2" -- -- Value Min. 200 200 -- -- 30 60 0 100 200 100 -- -- 30 60 -- -- -- -10 Typ. -- -- -- -- -- -- 120 -- -- -- -- -- -- -- 120 30 -- -- Max. -- -- 200 200 -- -- 300 -- -- -- 200 200 -- -- 300 100 50 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms V/s
* : Cascade connection enabled at 1.5 MHz. Load Conditions
* Load condition 1
Measurement point
* Load condition 2
Measurement point
CL = 20 pF to 100 pF
RAL = 10 k
CAL = 50 pF
12
MB40D001
* Input/Output Timing (CS method)
tCr CLK tCKL SI tSHD tCCH tCSH tCKH tCf
tSSU tCSU CS tSO SO
tSOD
tSOD
tSOZ
tPSU D0 D11 (at input) tPOD D0 D11 (at output) tAOD AO1 AO12
tPHD
90 % 10 %
CLK, SI, CS, SO D0 to D3 decision level is 80% and 20% of VccD. D4 to D11 decision level is 80% and 20% of VccA. AO1 to AO12 decision level is 90% and 10% of VccA.
13
MB40D001
s DATA INPUT/OUTPUT TIMING (Serial Bus Format)
* Timing of D/A Converter Operation, I/O Expander Operation (serial to parallel conversion), and ESR Write Operation.
SI
D0
D1
D2
DE
DF
CLK
1
2
3
15
16
CS
AOx
Dxx
SO
Data input is enabled at the fall of the CS signal. 16-bit data is input, and executed by shift register command at the rise of CS. In D/A converter operation, analog output selected at the rise of CS is converted. In serial to parallel conversion, digital output selected at the rise of CS is converted. In ESR write operation, data is set in the ESR at the rise of [CS] and used to change pin states. * I/O Expander Operation (parallel to serial conversion)
SI
D0
DF
CLK
1
16
1
2
16
(Parallel to serial conversion command entered) CS
Dxx Parallel data loaded SO D0 DF
(Parallel to serial conversion result output)
Data input is enabled at the fall of the CS signal. 16-bit data (parallel to serial conversion command) is input, and commands received at the rise of CS. At the fall of CS the data from parallel input is loaded in the shift register from D4 to DF, and output from the SO pin timed to the fall of the CLK signal. 14
MB40D001
s USAGE PRECAUTIONS
1. Preventing Latch-Up
A condition known as "latch-up" may occur when the input or output pins of a CMOS IC device are exposed to voltages higher then VCCD or VCCA or lower than GND voltage, or when voltages are applied to the device in excess of rated values for VCCD, VccA, or VDD to GND voltages. Latchup produces a rapid increase in power supply current, and may result in thermal destruction of elements. Users should take sufficient precautions to ensure that absolute maximum ratings are not exceeded at any time during use.
2. Power Supply Pins
The power supply should be connected to the VCCD, VCCA, VDD, and GND terminals of the IC with as low an impedance as possible. In addition, it is recommended that ceramic capacitors of approximately 0.1 F be connected as bypass capacitors between the VCCD, VCCA, and VDD terminals and the GND terminals.
s ORDERING INFORMATION
Part number MB40D001PFV Package 24-pin Plastic SSOP (FPT-24P-M03) Remarks
15
MB40D001
s PACKAGE DIMENSIONS
24-pi plastic SSOP (FPT-24P-M03)
* 7.750.10(.305.004)
*: These dimensions do not include resin protrusion.
1.25 -0.10 .049 -.004
+0.20 +.008
(Mounting height)
0.10(.004)
* 5.600.10
INDEX (.220.004)
7.600.20 (.299.008)
6.60(.260) NOM
0.650.12(.0256.0047)
0.22 -0.05 .009
+0.10 +.004 -.002
"A"
0.15 -0.02 .006 -.001
+0.05 +.002
Details of "A" part 0.100.10(.004.004) (STAND OFF)
7.15(.281)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F24018S-2C-2
Dimension in mm (inches)
16
MB40D001
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-fme.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F0001 (c) FUJITSU LIMITED Printed in Japan

▲Up To Search▲

Price & Availability of MB40D001PFV

	To Download MB40D001PFV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .